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? 1 ? e02y60-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD3531R 176 pin lqfp (plastic) description the CXD3531R incorporates digital signal processor type rgb driver, color shading correction and timing generator functions onto a single ic. operation is possible with a system clock up to 100 [mhz] (max.). this ic can process video signals in bands up to 100mhz, and can output the timing signals for driving various sony lcd panels. features ? various picture quality adjustment functions such as user adjustment, white balance adjustment and gamma correction osd mix, black frame processing, mute and limiter functions lcd panel color shading correction function lcd panel vertical stripe correction function drives various sony data projector lcd panels drives sony dot/line inversion drive panel controls the cxa3562ar and cxa7004r sample- and-hold drivers line inversion and field inversion signal generation supports ac drive of lcd panels during no signal on-chip serial interface the data of gamma correction and color shading correction can be downloaded automatically from the external eeprom. applications lcd projectors and other video equipment structure silicon gate cmos ic absolute maximum ratings (v ss = 0v) supply voltage v dd v ss ? 0.5 to +2.5 v v de v ss ? 0.5 to +4.5 v v dda v ss ? 0.5 to +4.5 v input voltage v i v ss ? 0.3 to v de + 0.3 v output voltage v o v ss ? 0.3 to v de + 0.3 v storage temperature tstg ?55 to +125 c junction temperature tj 125 c recommended operating conditions supply voltage v dd 1.65 to 1.95 v v de 3.0 to 3.6 v v dda 3.0 to 3.6 v operating temperature topr ?20 to +75 c digital signal driver/timing generator note) company names and product names in this data sheet are trademarks or registered trademarks of the res pective company. www.datasheet.in
? 2 ? CXD3531R block diagram eeprom rscl clksel plldiv clkpol clkc vdin hdin ys ym r, g, bosd r, g, bin hsda hscl hsel rsda dsd 12 3 12 3 2 3 tg external rom i/f direct clear host i/f host controller register i/f clkout1 clkout2 clkout3 r, g, bout rgt, dwn gcfbin1, gcfbin2, gcfbin 3 ctrl hst, pst, hck1, hck2, dck1, dck2, dck3, dck4, dck5, dck6, enb, pcg, prg, shst, hd2, hd3, clr , clp, hd1, vst, vck, frp, xfrp, xrgt, po1, po2 pllstb xclr2 xclr3 pll www.datasheet.in
? 3 ? CXD3531R pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 96 97 98 99 100 101 102 103 104 105 106 107 108 133 134 135 136 137 138 139 140 141 142 143 144 121 122 123 124 125 126 127 128 129 130 131 132 109 110 111 112 113 114 115 116 117 118 119 120 91 92 93 94 95 rin11 rin10 rin9 v dd rin8 rin7 rin6 v de vss rin5 rin4 rin3 rin2 rin1 rin0 gin11 gin10 gin9 gin8 v de vss gin7 gin6 gin5 gin4 gin3 gin2 gin1 gin0 v dd bin11 bin10 v de vss bin9 bin8 bin7 bin6 bin5 bin4 bin3 bin2 bin1 bin0 rout10 rout9 rout8 v dd rout7 rout6 rout5 vss v de rout4 rout3 rout2 rout1 rout0 gout11 gout10 vss v de gout9 gout8 gout7 gout6 gout5 gout4 gout3 gout2 vss v de gout1 gout0 bout11 bout10 bout9 bout8 bout7 vss v de bout6 bout5 bout4 v dd bout3 bout2 bout1 bout0 vss v de clkout3 clkout2 clkout1 vss v de rscl rsda v dd hsda vss v de clkpol clkc clksel v de vss hsel hscl vdin hdin bosd1 bosd0 v de gosd1 gosd0 rosd1 rosd0 v dd vss ys ym v de xclr3 xclr2 test2 test1 trst pllstb plldiv v ssa v dda rout11 v de vss vst vck v dd shst xfrp xrgt clp clr enb v de po1 po2 vss hck1 hck2 dck1 dck2 dck3 dck4 v de dck5 dck6 frp hd1 vss hd2 hd3 v de hst pcg prg pst v dd dwn rgt v de vss gcfbin1 gcfbin2 gcfbin3 ctrl 145 146 147 148 149 150 152 153 154 155 156 157 158 159 160 162 163 164 165 166 167 168 169 170 172 173 174 175 176 151 161 171 www.datasheet.in
? 4 ? CXD3531R pin description pin no. symbol i/o description input pin processing for open status 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 rin11 rin10 rin9 v dd rin8 rin7 rin6 v de v ss rin5 rin4 rin3 rin2 rin1 rin0 gin11 gin10 gin9 gin8 v de v ss gin7 gin6 gin5 gin4 gin3 gin2 gin1 gin0 v dd bin11 bin10 v de v ss bin9 bin8 bin7 i i i ? i i i ? ? i i i i i i i i i i ? ? i i i i i i i i ? i i ? ? i i i red data input red data input red data input internal operation power supply red data input red data input red data input i/o power supply gnd red data input red data input red data input red data input red data input red data input green data input green data input green data input green data input i/o power supply gnd green data input green data input green data input green data input green data input green data input green data input green data input internal operation power supply blue data input blue data input i/o power supply gnd blue data input blue data input blue data input ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? www.datasheet.in
? 5 ? CXD3531R 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 bin6 bin5 bin4 bin3 bin2 bin1 bin0 v dda v ssa plldiv pllstb trst test1 test2 xclr2 xclr3 v de ym ys v ss v dd rosd0 rosd1 gosd0 gosd1 v de bosd0 bosd1 hdin vdin hscl hsel v ss v de clksel clkc clkpol i i i i i i i ? ? i i i i i i i ? i i ? ? i i i i ? i i i i i i ? ? i i i blue data input blue data input blue data input blue data input blue data input blue data input blue data input pll power supply pll gnd pll operation mode selection (h: 50mhz or less, l: 50mhz or more) pll standby pin (h: pll standby) test pin (connect to gnd.) test pin (connect to gnd.) test pin (connect to gnd.) external clear (l: reset) external clear (l: reset) i/o power supply osd ym input osd ys input gnd internal operation power supply osd red data input osd red data input osd green data input osd green data input i/o power supply osd blue data input osd blue data input horizontal sync signal input vertical sync signal input serial bus clock (host i/f) serial bus slave address selection signal input gnd i/o power supply internal clock selection (h: pll through, l: pll oscillation) clock input (cmos input) internal clock polarity selection (h: inverted, l: non-inverted) ? ? ? ? ? ? ? ? ? l ? l l l l l ? l l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? l ? l pin no. symbol i/o description input pin processing for open status www.datasheet.in
? 6 ? CXD3531R 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 v de v ss hsda v dd rsda rscl v de v ss clkout1 clkout2 clkout3 v de v ss bout0 bout1 bout2 bout3 v dd bout4 bout5 bout6 v de v ss bout7 bout8 bout9 bout10 bout11 gout0 gout1 v de v ss gout2 gout3 gout4 gout5 gout6 ? ? i/o ? i/o o ? ? o o o ? ? o o o o ? o o o ? ? o o o o o o o ? ? o o o o o i/o power supply gnd serial bus data i/o (host i/f) internal operation power supply serial bus data i/o (external rom i/f) serial bus clock i/o (external rom i/f) i/o power supply gnd internal clock output (inverted output) internal clock output (inverted output) internal clock output (inverted output) i/o power supply gnd blue data output blue data output blue data output blue data output internal operation power supply blue data output blue data output blue data output i/o power supply gnd blue data output blue data output blue data output blue data output blue data output green data output green data output i/o power supply gnd green data output green data output green data output green data output green data output ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pin no. symbol i/o description input pin processing for open status www.datasheet.in
? 7 ? CXD3531R 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 gout7 gout8 gout9 v de v ss gout10 gout11 rout0 rout1 rout2 rout3 rout4 v de v ss rout5 rout6 rout7 v dd rout8 rout9 rout10 rout11 v de v ss vst vck v dd shst xfrp xrgt clp clr enb v de po1 po2 v ss o o o ? ? o o o o o o o ? ? o o o ? o o o o ? ? o o ? o o o o o o ? o o ? green data output green data output green data output i/o power supply gnd green data output green data output red data output red data output red data output red data output red data output i/o power supply gnd red data output red data output red data output internal operation power supply red data output red data output red data output red data output i/o power supply gnd vertical display start timing pulse output vertical display transfer clock output internal operation power supply shst output ac drive inversion timing pulse output (reversed polarity of frp) horizontal scan direction switching signal output (reversed polarity of rgt) clp pulse output clr pulse output gate enable pulse output i/o power supply parallel output 1 parallel output 2 gnd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pin no. symbol i/o description input pin processing for open status www.datasheet.in
? 8 ? CXD3531R 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 hck1 hck2 dck1 dck2 dck3 dck4 v de dck5 dck6 frp hd1 v ss hd2 hd3 v de hst pcg prg pst v dd dwn rgt v de v ss gcfbin1 gcfbin2 gcfbin3 ctrl o o o o o o ? o o o o ? o o ? o o o o ? i/o i/o ? ? i i i i horizontal display transfer clock output 1 horizontal display transfer clock output 2 dck1 pulse output dck2 pulse output dck3 pulse output dck4 pulse output i/o power supply dck5 pulse output dck6 pulse output ac drive inversion timing pulse output horizontal auxiliary pulse output 1 gnd horizontal auxiliary pulse output 2 horizontal auxiliary pulse output 3 i/o power supply horizontal display start timing pulse collective precharge timing pulse output 2-step precharge timing pulse output dot sequential precharge start timing pulse output internal operation power supply vertical scan direction switching signal i/o horizontal scan direction switching signal i/o i/o power supply gnd gcfbin pulse input 1 gcfbin pulse input 2 gcfbin pulse input 3 scan direction control method switching (l: internal register, h: external) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? l pin no. symbol i/o description input pin processing for open status www.datasheet.in
? 9 ? CXD3531R electrical characteristics dc characteristics (topr = ?20 to +75c, v ss = 0v) ? 1 input pins other than those indicated in items input voltage 2 and input voltage 3. ? 2 tj [c] toprmax [c] + ja [c/w] pd [w]. ac characteristics (topr = ?20 to +75c, v dd = 1.8 0.15v, v de = 3.3 0.3v, v ss = 0v) supply voltage input voltage 1 input voltage 2 output voltage power consumption v dd v de v ih1 v il1 v ih2 v il2 v oh v ol pd ? 2 ? ? ? 1 hdin, vdin, hscl, hsda, rscl, rsda all output pins ? ? ? cmos input cell cmos schmitt trigger input cell ? ? clkc = 100mhz 1.65 3.0 2.0 ? 0.7v de ?0.3 v de ? 0.4 ? ? 1.8 3.3 ? ? ? ? ? ? ? 1.95 3.6 ? 0.8 v de + 0.3 0.2v de ? 0.4 1100 item symbol applicable pins conditions min. typ. max. v mw unit ? 3 output pins other than frp, xfrp, shst and prg. clock input period input setup time input hold time input setup time input hold time output rise/fall delay time output rise/fall delay time cross-point time difference hck1 duty hck2 duty phase compensation pll operating frequency ? tis tih tis tih tor/tof tor/tof ? t th/(th + tl) tl/(th + tl) ? clkc rgb input, osd input, hdin, vdin hscl, hsda, rsda ? 3 frp, xfrp, shst, prg hck1, hck2, dck1, dck2, dck3, dck4, dck5, dck6 hck1 hck2 ? ? ? ? ? ? cl = 20pf cl = 50pf cl = 20pf cl = 20pf cl = 20pf 10.0 2.0 2.0 5.0 5.0 1.0 1.0 ?5.0 48 48 ? ? ? ? ? ? ? ? 50 50 ? ? ? ? ? 7.0 7.0 5.0 52 52 ns % mhz item symbol applicable pins conditions min. typ. max. unit plldiv = v plldiv = h 50 25 ? ? 100 55 www.datasheet.in
? 10 ? CXD3531R timing definition power-on and initialization of internal circuit as for this ic, two systems of supply voltage should be turned on simultaneously. the initialization of the internal circuit should be also performed by maintaining the system clear pin at low during the specified time after setting the supply voltage in the range of recommended operating conditions and stabilizing as shown in the figure below. keep in mind that the internal circuit may not be initialized correctly if system clear cancellation is performed before the supply voltage is set in the range of the recommended operating conditions. v dd , v d e vss v de vss v de vss pllstb v dd , v de tr tr > 200ns xclr2 xclr3 > 300s v oh v ol v oh v ol hck1, dck1, dck3, dck5 hck2, dck2, dck4, dck6 50% 50% 50% ? t 50% ? t v oh v ol hck1, hck2 50% th tl 50% 50% 50% v ih1 v il1 v ih1 , v ih 2 v il1 , v il 2 v ih1 v il1 v oh v ol v oh v ol v oh v ol 50% 50% 50% 50% 50% tor tof tor tih tis tof clkc clkc clkout1 clkout2 clkout3 h din, vdin r gb input, osd input outputs other than clkout outputs other than clkout www.datasheet.in
? 11 ? CXD3531R description of operation 1. description of input pins (a) initializing pins (pllstb, xclr2 and xclr3) internal pll is initialized by setting pllstb (pin 48) to 1 and internal circuit is initialized by setting xclr2 (pin 52) to 0. in addition, rgb output is initialized (preset) by setting xclr3 (pin 53) to 0. initialization should be performed when power is turned on. be sure to perform power supply on according to an initialization procedure. (b) sync signal input pins (hdin and vdin) horizontal and vertical separate sync signals are input to hdin (pin 66) and vdin (pin 67), respectively. the CXD3531R supports only non-interlace sync signals with a dot clock of 100mhz or less. (c) master clock input pins (clkc, clksel and clkpol) phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. the master clock input pin has clkc (pin 73) for cmos level input. clkpol: 0 = input clock is non-inverted; 1 = input clock is inverted clksel: 0 = pll oscillation; 1 = pll through (d) pll setting pin (plldiv) plldiv (pin 47) sets the divider setting of the internal phase compensation pll circuit. the setting values for master clock frequency are as follows. plldiv: 0 = 55 to 100mhz; 1 = 25 to 50mhz note that the frequency of the clock input to the CXD3531R must be within the phase compensation pll operating range, even during free running. (e) rgb signal input pins (rin, gin and bin) these pins input rgb digital signals in 12 bits. the red signal is input to rin (pins 1 to 3, 5 to 7 and 10 to 15), the green signal to gin (pins 16 to 19 and 22 to 29), and the blue signal to bin (pins 31, 32 and 35 to 44) respectively. rin0, gin0 and bin0 are lsb, and rin11, gin11 and bin11are msb respectively. (f) osd signal input pins (rosd, gosd, bosd, ys and ym) these pins input osd signals. the red signal is input to rosd (pins 59 and 60), the green signal to gosd (pins 61 and 62), and the blue signal to bosd (pins 64 and 65) respectively. in addition, the ym signal is input to ym (pin 55), and the ys signal to ys (pin 56). www.datasheet.in
? 12 ? CXD3531R (g) host serial clock input pin (hscl) hscl (pin 68) is the clock input pin used to set the i/o timing for serial data from the host. data is taken from the hsda pin when the clock signal rises, and data is output to the hsda pin when the clock signal falls. (h) host serial i/o pin (hsda) this is the i/o pin for serial data from the host. the output is an open drain, so this pin must be pulled up using an external resistor. it is necessary to switch the input to the hsda (pin 77) while the signal level of hscl is low. (i) device address input pin (hsel) simultaneous connection of this ic can be made up to two ics on the same serial bus. since a device address is used to identify each of these devices, this pin should be connected to 1 or 0 externally. this 1 and 0 setting drives the device which matches the slave address input from the hsda pin. when two ics are used simultaneously, choose a different device address. the slave addresses of this ic used for the hsel (pin 69) setting are as follows. hsel: 0 = 74h; 1 = 76h (j) external eeprom serial clock output pin (rscl) rscl (pin 80) is the clock output pin used to set the i/o timing of serial data sent to the external eeprom. the output is an open drain, so this pin must be pulled up using an external resistor. data is taken from the rsda pin when the clock signal rises, and data is output to the rsda pin when the clock signal falls. (k) external eeprom serial i/o pin (rsda) this is the i/o pin for serial data sent to the external eeprom. the output is an open drain, so this pin must be pulled up using an external resistor. also, it is necessary to switch the input to the rsda (pin 79) while the signal level of rscl is low. (l) scan direction control system switching pins (rgt, dwn, ctrl) the i/o direction of the lcd panel scan direction switching pins rgt (pin 170) and dwn (pin 169) is set by ctrl (pin 176). ctrl: 0 = rgt and dwn are output pins, 1 = rgt and dwn are input pins when ctrl = 0, rgt and dwn output the respective register setting values. when ctrl = 1, the externally set values are input to rgt and dwn and reflected to the internal operation. www.datasheet.in
? 13 ? CXD3531R (m) gcfb pulse input pins (gcfbin) the gcfbin (pins 173, 174 and 175) input the lcd panel internal signal latch pulse. set these pins according to the register setting procedure during power-on and at set intervals. (n) test pins (trst, test) trst (pin 49) and test (pins 50 and 51) are test pins. leave these pins open, or connect them to gnd. 2. pipeline delay of the rgb and osd signals the pipeline delay for the i/o of the rgb signals is 46 clock cycles of the master clock. in addition, the pipeline delay for the osd, ys and ym signals is 39 clock cycles of the master clock. www.datasheet.in
? 14 ? CXD3531R 3. serial bus the serial bus of this ic consists of a host i/f, external rom i/f and register i/f. 3-1. host i/f with this ic, each register setting and data set to built-in ram are performed over a serial bus. bus protocol conforms to i 2 c bus specifications. also, when accessing gamma ram, always access memory address from odd addresses in 2-byte units. the following restrictions are placed on the host i/f of this ic. only i 2 c bus slave operations are performed. standard mode and fast mode are supported. hs mode is not supported. the general call address and start byte of the slave address are not acknowledged. c bus compatibility is not supported. acknowledgment is not performed for 10-bit slave addresses. low is not asserted for hscl. (wait control is not performed.) (1) "start" conditions read and write operations enter "start" status by switching hsda input from high to low level while hscl input is high. (2) "stop" conditions "stop" results by switching hsda input from low to high while hscl input is high. setting "stop" status causes read processing to terminate during read operations, and causes the input of write data to terminate during write operations. h sda h scl "start" "stop" "start" conditions and "stop" conditions www.datasheet.in
? 15 ? CXD3531R (4) device address specification after "start" is sent, a 7-bit slave address and 1-bit read/write code is sent. read/write operations with this ic start if the input slave address matches the device address set using hsel. if the device address does not match, "acknowledgment" is not generated and the system does nothing. (5) byte write operation after "start" is sent, the r/w code is set to low and an 8-bit device address word is input. the ic outputs "acknowledgment" on the 9th bit and enters write mode. after this, "acknowledgment" is output every 8 bits after each of the two 8-bit memory addresses are input. next, "acknowledgment" is output after 8 bits of write data is input and written to the ic. a15 s ta rt h sda 1st memory address (n) 2nd memory address (n) write data (n) slave address hsel r/w ack ack ack ack stop 1w 0 1 1 1 0 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 byte write operation hsda in h sda out 12 89 " acknowledgment " "start" hscl acknowledged not acknowledged (3) acknowledgment (ack) acknowledgment is used to indicate whether or not data has been sent/received normally. the "acknowledgment" of a data transfer is performed after that data transfer when the sender releases the bus on the 9th clock of hscl and the receiver drives low. if the host is the receiver, the ic is informed by the host that data has ended by the fact that "acknowledgment" is not generated for the last data sent from the ic. acknowledgment on the i 2 c bus ? if r/w = 1, read results, if r/w = 0, write results. 0 1 1 1 0 1 hsel r/w device address word (8 bits) device select r/w code device code (fixed) device address specification www.datasheet.in
? 16 ? CXD3531R (7) byte read operation after "start" is sent, the r/w code is set to low and an 8-bit device address word is input. the ic outputs "acknowledgment" to the 9th bit and enters write mode. after this, "acknowledgment" is output every 8 bits after each of the two 8-bit memory addresses are input. once the addresses are acknowledgment, "restart" is input, and the r/w code is set to high, an 8-bit device address word is input, and the ic outputs "acknowledgment" to the 9th bit and enters read mode. next, 8 bits of read data are output using the address used for the dummy write, and the read operation terminates if "stop" is input without inputting "acknowledgment". a15 start h sda 1st memory address (n) dummy write 2nd memory address (n) slave address hsel r/w ack ack ack 1w 0 1 1 1 0 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 slave address read data (n) hsel restart r/w ack no ack stop 1r 0 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 current address read byte read operation a15 start h sda 1st memory address (n) 2nd memory address (n) write data (n) slave address hsel r/w ack ack ack ack 1w 0 1 1 1 0 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write data (n + m) ack ack stop d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 (6) continuous write operation this ic possesses a function which can write data continuously. with the continuous write operation, write data is written in a manner similar to the byte write operation. continuous write is possible by sending write data continuously before sending "stop". the address used to write data during the continuous write operation is automatically incremented when each separate write operation terminates. there is no limit on the number of continuous transfers that are possible to write continuously with this ic. continuous write operation www.datasheet.in
? 17 ? CXD3531R d7 start or r estart slave address read data (n) read data (n + 1) read data (n + m) hsel r/w ack ack ack no ack stop 1r 0 1 1 1 0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 (8) continuous read operation this ic possesses a function which can read data continuously. with the continuous read operation, data up to the current address is read in a manner similar to the byte read operation. continuous read is possible by receiving continuous read data and perform "acknowledgment" before sending "stop". the address used for reading data during the continuous read operation is automatically incremented when each separate read operation terminates. there is no limit on the number of continuous transfers that are possible to read continuously with this ic. continuous read operation www.datasheet.in
? 18 ? CXD3531R 3-2. conditions for accessing gamma ram and color shading ram with this ic, there are two way to access the internal ram: by the host i/f using the i 2 c bus and refresh/write- back for sending/receiving data via external rom i/f. in the case of gamma ram, internal ram must be accessed by the host i/f in 2-byte units, and memory address must be read from or written to even memory addresses. color shading ram can be accessed in 1-byte units and there is no restriction on which addresses can be read or written. it is possible to access internal ram from each i/f when the conditions given in the following table are established. gam_on 0 1 1 vertical blanking period ? vertical blanking period outside vertical blanking period gamma ram access ye s ye s no ? gam_on represents the setting value of the dsd register. ? gamma correction is not performed when gam_on is "0", and is performed when gam_on is "1". conditions for accessing gamma ram csc_on 0 1 1 vertical blanking period ? vertical blanking period outside vertical blanking period color shading ram access ye s ye s no ? csc_on represents the setting value of the color shading register. ? color shading correction is not performed when csc_on is "0", and is performed when csc_on is "1". conditions for accessing color shading ram gam_on must be set to "0" when performing a write-back or forced refresh operation for gamma ram. similarly, csc_on must be set to "0" when performing a write-back or forced refresh operation for color shading ram. in the case of a self-refresh operation, the start of vertical blanking period is automatically detected and operations start automatically at that time, regardless of how gam_on and csc_on are set. therefore, be sure to set the external i 2 c rom transfer count register rom_tran to fit within the vertical blanking period. furthermore, the vertical blanking period for gamma is set using csc_hp, csc_vp, csc_hnum, csc_vnum, csc_hint and csc_vint. make all settings in accordance with the specifications of the video signal attempting to be displayed. www.datasheet.in
? 19 ? CXD3531R 3-3. external rom i/f when operating the external rom i/f, operations start by setting the serial bus register from the host i/f. the serial bus on the rom side is used to access the external eeprom that comforms to i 2 c bus. bus protocol conforms to i 2 c bus specifications. also, the following restrictions are placed on the external eeprom i/f of this ic. only master operations are performed. standard mode and fast mode are supported. hs mode is not supported. multi-master functions are not supported. the general call address and start byte of the slave address are not generated. c bus compatibility is not supported. a memory address space of up to 512k bytes is supported. wait control by rscl is not supported. 10-bit slave addresses are not supported. (1) external rom i/f clock settings the frequency of the clock signal supplied to the external eeprom by the rscl pin is set using rscl_sel of the serial bus control registers. set this value based on the operating frequency of the ic as given in the table below so that the frequency output by the rscl pin is appropriate for the specifications of the external eeprom. rscl_sel 00 01 10 11 frequency formula of rscl output f/2 7 f/2 8 f/2 9 f/2 10 ? enters operating frequency of this ic in "f" in the table. example) when operating frequency is 100mhz (rscl_sel = 01) 100 10 3 /2 8 = 390.625khz (2) external eeprom memory capacity setting with this ic, slave addresses and memory addresses are generated in accordance with the memory capacity set for the external eeprom. the memory capacity of the external eeprom is set using rom_map of the serial bus control registers. rom_map 00 01 10 11 usable memory size 512k-bit (65,536 8-bit) 256k-bit (32,768 8-bit) 128k-bit (16,384 8-bit) 64k-bit (8,192 8-bit) www.datasheet.in
? 20 ? CXD3531R [example] address output when using eight 256k-bit eeproms (rom_map = 01) with this ic, the rom slave address register setting [7:4] is set as is for the serial bus slave address [7:4], and the memory address [17:15] is used for the slave address [3:1]. the memory address [14:0] is used as is for the 1st and 2nd memory addresses. the 1st memory address [7] is fixed to all "0". furthermore, up to eight external eeproms can be connected to this ic. b ank0 eeprom 256k-bit eeprom 256k-bit eeprom 256k-bit bank1 x0h rsda rscl x1h x7h bank7 CXD3531R bank0 32k-byte 32k-byte 32k-byte x0h slave addres s x1h x7h 0_0000h 0 _7fffh 0_8000h 0 _ffffh 1_0000h 3 _7fffh 3_8000h 3 _ffffh bank1 bank7 s lave address register [7:1] s lave address register [7:4] memory address [18:0] 1st memory address [7:0] 2nd memory address [7: 0] 74 0 118 71 7 0 0 70 system configuration diagram memory map 256k-byte space www.datasheet.in
? 21 ? CXD3531R (3) external rom i/f slave address setting the external rom i/f of this ic transfers data into and out of memory using the serial bus as host i/f. since operations conform to i 2 c bus protocol just as with the host i/f, this section only describes the slave address. to access the external eeprom, when access conditions are established, "start" is sent, and then 7 bits representing the slave address are output, and the r/w code is output. "acknowledgment" is received to the 9th bit from the external eeprom, and the ic enters either read or write mode. the slave address is determined based on rom_map of the serial bus rom i/f control register and rslv_addr of the serial bus rom slave address register as previously described. the user should set the upper 4 bits of the device address of the eeprom to be used in rslv_addr and the memory size in rom_map. this allows memory to be used without awareness of memory boundaries of actual memory used for the setting memory space. a15 s ta rt r sda 1st memory address (n) 2nd memory address (n) write data (n) slave address r/w ack ack ack ack stop w a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 byte write operation (4) memory location and data size setting for the external eeprom since this ic performs refresh and write-back operations, it is necessary to set which addresses of the external eeprom gamma data and color shading data have been located in. the registers used to make these settings are the serial bus rom gamma data start address register and the i 2 c rom color shading data start address register. by specifying the starting position of the data area in these registers data access from the specified addresses is possible during refresh and write-back operation. units of 1k-byte can be used to set the start addresses which can be set in these registers. in addition, the size of data transferred during refresh and write-back operations is fixed at 2k bytes for each color in the case of gamma data. the number of bytes transferred in the case of color shading data is the value stored in the color shading data size register plus one. www.datasheet.in
? 22 ? CXD3531R (5) refresh and write-back operations this ic includes a function that allows an external eeprom to automatically refresh the internal ram. this function has the four modes described below. self-refresh mode forced refresh mode write-back mode refresh stop mode each mode is started by writing the specified mode into ref_mode of the refresh register. in self-refresh mode, the ic detects that the vertical blanking period has been entered and, using the value specified in the i 2 c rom transfer count register, uses the continuous read operation to transfer data of the size "transfer count plus 1" to the external eeprom i/f. the data read using the continuous read transfer is written into the internal ram. when the transfer of the all data for the data size is completed, the access area for the internal ram is changed, continuous read transfer is executed indefinitely until self-refresh mode is exited, and refresh operations are automatically carried out on the internal ram. also, refresh area can be selected by ref_area setting. in forced refresh mode, continuous read transfer from the external eeprom is performed for the ram area specified by ref_rsel of the refresh ram select register, and the read data is written to the internal ram. when the transfer of all data for the specified ram area is completed, ref_end of the refresh status register set to a flag indicating the operation has ended, and operations stop. if forced refresh operations are to be performed for the entire internal ram, first set the refresh ram select register to gamma ram (r) and perform the forced refresh operation. since the refresh ram select register is automatically set to the next ram area after all data is transferred, refresh for the entire ram can be completed by repeating the forced refresh operation five times. in write-back mode, continuous write transfer is performed from the ram area specified by ref_rsel of the refresh ram select register to the external eeprom. when the transfer of all data for the specified ram area is completed, ref_end of the refresh status register set to a flag indicating the operation has ended, and operations stop. if write-back operations are to be performed for the entire internal ram, first set the refresh ram select register to gamma ram (r) just as for forced refresh operation, and then perform the write-back operation. since the refresh ram select register is automatically set to the next ram area after all data is transferred, write-back for the entire ram can be completed by repeating the write-back operation five times. in refresh stop mode, the external rom i/f does not operate and nothing is output on the serial bus. (6) forced reset of the external rom i/f control circuit with this ic, forced reset is possible in case a problem occurs with the external rom i/f and the internal circuit becomes locked. forced reset initializes only the external rom i/f control circuit by writing "1" to rom_rst of the refresh register. normal operations are allowed after initialization is complete. 3-4. register i/f control circuit the register i/f control circuit transfers data between the host i/f and the external rom i/f. register data other than ram data is stored here. since registers have a double buffer configuration, data in the first buffer is synchronized with the internal vd and reflected in the second buffer, while data in the second buffer is input to each block. note, however, that data in the serial bus control register has a single buffer configuration. www.datasheet.in
? 23 ? CXD3531R 3-5. software flow (1) settings when power is turned on the following procedure is the setting procedure first performed after power of the ic is turned on. if this procedure is not executed, the internal vd will not be generated and register data cannot be set correctly. since the tg register uses a double register configuration using a v latch, set the force_vd register of the serial bus control register to "1" only at startup to transfer tg register setting values. start end perform setting for unset registers. if tg is operating at this time, there is no need to write the force_vd register due to the fact that registers having a double register configuration will be automatically written using vd from an external source. perform settings such as for the timing of the corresponding lcd panel using the tg register. (2) setting procedure of the serial bus control register the following procedure is the procedure for setting the serial bus control register in accordance with the external eeprom to which the ic is connected. be sure to make settings according to the operating frequency of the ic and the speed, capacity and number of external eeproms that are connected. find the optimum clock frequency for the external rom i/f based on the frequency of the system clock and set the bits 1 and 0 of the rscl_sel register to this value. start end set the total capacity of the connected eeprom devices and set bits 5 and 4 of the rom_map register to this value. set the slave addresses of the eeprom devices connected into the rslv_addr register. set the area where write-back and refresh operations are performed to bits 1 and 0 of the ref_area register. www.datasheet.in
? 24 ? CXD3531R (3) write-back procedure the following procedure is the procedure for writing gamma correction and color shading correction data back to the external eeprom. during display, mute the video signal using the dsd register. write "1" to the ref_end register and clear status. set the gam_addr, csc_addr, csc_size and rom_tran registers to the addresses and transfer count to be used to perform write-back. start end set gam_on = 0 and csc_on = 0 so that the gamma rams and color shading rams are not used . read the ref_end register. write data into the gamma rams (r, g, b) and color shading rams (r, g, b). write "1" to the ref_end register and clear status. write 03h to the ref_mode register to start write-back . ye s 1: write-back complete no is the status "1"? read the ref_rsel register. is write-back complete for all rams? end is there other gamma and color shading data to be written back? 0: write-back currently being performed write-back other data. set the ref_rsel register to gamma ram (r). www.datasheet.in
? 25 ? CXD3531R (4) forced refresh procedure during power-on the following procedure is the procedure for setting gamma correction and color shading correction data from an external eeprom for forced refresh when power is turned on. during display, mute the video signal using the dsd register. write "1" to the ref_end register and clear status. set the gam_addr, csc_addr, csc_size and rom_tran registers to the addresses and transfer count to be used to perform forced refresh. start end set gam_on = 0 and csc_on = 0 so that the gamma rams and color shading rams are not used. read the ref_end register. set the ref_rsel register to gamma ram (r). write "1" to the ref_end register and clear status. write 02h to the ref_mode register to start forced refresh. set gam_on and csc_on so that the gamma rams and color shading rams will be used by the video signal . ye s 1: forced refresh comple te no if a video signal is to be displayed, cancel muting of the video signal using the dsd register. is the status "1"? read the ref_rsel register. is forced refresh complete for all rams? 0: forced refresh currently being performed www.datasheet.in
? 26 ? CXD3531R (5) procedure for forced refresh during normal operations the following procedure is the procedure for selecting either gamma correction or color shading correction data during normal operations. during display, mute the video signal using the dsd register. write "1" to the ref_end register and clear status. set the gam_addr and rom_tran registers to the addresses and transfer count to be used to perform forced refresh. start end set gam_on = 0 so that the gamma rams are not used. read the ref_end register. set the ref_rsel register to gamma ram (r). write "1" to the ref_end register and clear status. write 02h to the ref_mode register to start forced refresh. forced refresh complete for all gamma rams. 1: forced refresh complete p erform forced r efresh for the other g amma rams. if a video signal is to be displayed, cancel muting of the video signal using the dsd register. is the status "1"? read the ref_rsel register. is forced refresh of the gamma rams (r, g, b) complete? 0: forced refresh currently being performed during display, mute the video signal using the dsd register. write "1" to the ref_end register and clear status. set the csc_addr, csc_size and rom_tran registers to the addresses and transfer count to be used to perform forced refresh. start end set csc_on = 0 so that the color shading rams are not used. read the ref_end register. set the ref_rsel register to color shading ram (r). write "1" to the ref_end register and clear status. write 02h to the ref_mode register to start forced refresh. set gam_on so that the color shading rams will be used by the video signal. set gam_on so that the gamma rams will be used by the video signal. forced refresh complete for all color shading ram s. 1: forced refresh complete perform forced refresh for the other color shading rams. if a video signal is to be displayed, cancel muting of the video signal using the dsd register. is the status "1"? read the ref_rsel register. is forced refresh of the color shading rams (r, g, b) complete? 0: forced refresh currently being performed www.datasheet.in
? 27 ? CXD3531R (6) procedure for self-refresh during normal operations starting the refresh operation the following procedure is the procedure used to set cyclic refreshing of the gamma correction and color shading correction data stored in the built-in ram during normal operations. set the gam_h1, gam_h2, gam_v1 and gam_v2 registers of the dsd register and the csc_hnum, csc_vnum, csc_hint and csc_vint registers of the color shading register to the appropriate values. start end set gam_on and csc_on so that the gamma rams and color shading rams are used by the video signal. set the gam_addr, csc_addr, csc_size and rom_tran registers to the addresses and transfer count to be used to perform self-refresh. set the ref_rsel register to gamma ram (r). write "1" to the ref_end register and clear status. write 01h to the ref_mode register and start self-refresh. stopping the refresh operation the following procedure is the procedure used to stop the self-refresh operation. start end write 00h to the ref_mode register to stop self-refresh. www.datasheet.in
? 28 ? CXD3531R notes on handling the power supply and gnd patterns have a large effect on undesired radiation on the substrate and interference to analog circuits, etc. general precautions are as follows. make the gnd pattern as wide as possible. using a multi-layer substrate and a solid ground is recommended. connect each power supply pin to gnd via a ceramic chip capacitor of 0.1f or more located as close to each pin as possible. do not use this ic under conditions other than the recommended operating conditions. absolute maximum rating values should not be exceeded even momentarily. exceeding that ratings may damage the device, leading to eventual breakdown. this ic has a mos structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. since this ic utilizes a mos structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the i/o pins, interface with two power supplies of another circuit, or the order in which power is supplied to circuits. make a thorough study of measures against the possibility of latch up before use. when the initialization of this ic is performed at power-on, system clear cancellation is performed after the supply voltage is set in the range of the recommended operating conditions and stabilized. keep in mind that the internal circuit may not be initialized correctly if system clear cancellation is performed before the supply voltage is set in the range of the recommended operating conditions. when designing the substrate, take sufficient care for the surrounding temperature and heat radiation, and make sure the ic junction temperature does not exceed the maximum value. be sure to make the number of dot clocks input to the CXD3531R in 1h an even number. note that if there is an odd number of dot clocks, the internal phase compensation pll will not operate properly. be sure to make a thorough evaluation of any items not listed in this data sheet. www.datasheet.in
? 29 ? CXD3531R application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 96 97 98 99 100 101 102 103 104 105 106 107 108 133 134 135 136 137 138 139 140 141 142 143 144 121 122 123 124 125 126 127 128 129 130 131 132 109 110 111 112 113 114 115 116 117 118 119 120 91 92 93 94 95 rin11 rin10 rin9 v dd rin8 rin7 rin6 v de vss rin5 rin4 rin3 rin2 rin1 rin0 gin11 gin10 gin9 gin8 v de vss gin7 gin6 gin5 gin4 gin3 gin2 gin1 gin0 v dd bin11 bin10 v de vss bin9 bin8 bin7 bin6 bin5 bin4 bin3 bin2 bin1 bin0 rout10 rout9 rout8 v dd rout7 rout6 rout5 vss v de rout4 rout3 rout2 rout1 rout0 gout11 gout10 vss v de gout9 gout8 gout7 gout6 gout5 gout4 gout3 gout2 vss v de gout1 gout0 bout11 bout10 bout9 bout8 bout7 vss v de bout6 bout5 bout4 v dd bout3 bout2 bout1 bout0 vss v de clkout3 clkout2 clkout1 vss v de rscl rsda v dd hsda vss v de clkpol clkc clksel v de vss hsel hscl vdin hdin bosd1 bosd0 v de gosd1 gosd0 rosd1 rosd0 v dd vss ys ym v de xclr3 xclr2 test2 test1 trst pllstb plldiv v ssa v dda rout11 v de vss vst vck v dd shst xfrp xrgt clp clr enb v de po1 po2 vss hck1 hck2 dck1 dck2 dck3 dck4 v de dck5 dck6 frp hd1 vss hd2 hd3 v de hst pcg prg pst v dd dwn rgt v de vss gcfbin1 gcfbin2 gcfbin3 ctrl 145 146 147 148 149 150 152 153 154 155 156 157 158 159 160 162 163 164 165 166 167 168 169 170 172 173 174 175 176 151 161 171 ctrl hsda scl sda external cp u external eeprom blue output red output green output blue output clock output osd output clkc vdin hdin xclr3 xclr2 pllstb hscl 0.1 10 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 blue input green input red input gnd 0.1 0.1 0.1 0.1 0.1 0.1 3.3k +3.3v 3.3k 3.3k 3.3k +3.3v 1.8v 0.1 0.1 0.1 0.1 0.1 0.1 clkpol clksel hsel plldiv 10 +3.3v red output tg output g cfbin pulse input +3.3v www.datasheet.in
? 30 ? CXD3531R sony corporation package outline unit: mm detail a package material lead treatment lead material package mass epoxy resin copper alloy package structure 1.8g 176pin lqfp (plastic) 24.0 0.1 132 26.0 0.2 89 88 45 44 1 0.5 b 1.7 max 1.4 0.1 b a m 0.1 0.10 sony code eiaj code jedec code lqfp-176p-l01 p-lqfp176-24x24-0.5 133 176 s s s (25.0) (0.5) 0? to 10? 0.1 0.05 0.6 0.15 0.25 solder plating (0.125) 0.145 0.04 (0.2) detail b : solder b=0.22 0.05 l ead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec. www.datasheet.in

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